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? intel corporation, 1996 june 1996 order number: 272886-001 a preliminary 80960cf-40, -33, -25, -16 32-bit high-performance superscalar embedded microprocessor ? socket and object code compatible with 80960ca ? two instructions/clock sustained execution ? four 71 mbytes/s dma channels with data chaining ? demultiplexed 32-bit burst bus with pipelining n 32-bit parallel architecture two instructions/clock execution load/store architecture sixteen 32-bit global registers sixteen 32-bit local registers manipulates 64-bit bit fields 11 addressing modes full parallel fault model supervisor protection model n fast procedure call/return model full procedure call in 4 clocks n on-chip register cache caches registers on call/ret minimum of 6 frames provided up to 15 programmable frames n on-chip instruction cache 4 kbyte two-way set associative 128-bit path to instruction sequencer cache-lock modes cache-off mode n high bandwidth on-chip data ram 1 kbyte on-chip data ram sustains 128 bits per clock access n selectable big or little endian byte ordering n four on-chip dma channels 71 mbytes/s fly-by transfers 40 mbytes/s two-cycle transfers data chaining data packing/unpacking programmable priority method n 32-bit demultiplexed burst bus 128-bit internal data paths to and from registers burst bus for dram interfacing address pipelining option fully programmable wait states supports 8-, 16- or 32-bit bus widths supports unaligned accesses supervisor protection pin n high-speed interrupt controller up to 248 external interrupts 32 fully programmable priorities multi-mode 8-bit interrupt port four internal dma interrupts separate, non-maskable interrupt pin context switch in 625 ns typical n on-chip data cache 1 kbyte direct-mapped, write through 128 bits per clock access on cache hit
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preliminary iii a contents 80960cf-40, -33, -25, -16 32-bit high-performance superscalar embedded microprocessor 1.0 purpose .................................................................................................................................................. 1 2.0 80960cf overview ................................................................................................................................ 1 2.1 the 80960c-series core .................................................................................................................... 3 2.2 pipelined, burst bus ........................................................................................................................... 3 2.3 instruction set summary .................................................................................................................... 3 2.4 flexible dma controller ...................................................................................................................... 3 2.5 priority interrupt controller .................................................................................................................. 4 3.0 package information ........................................................................................................................ 5 3.1 package introduction .......................................................................................................................... 5 3.2 pin descriptions .................................................................................................................................. 5 3.3 80960cf mechanical data ............................................................................................................... 12 3.3.1 80960cf pga pinout ......................................................................................................... 12 3.3.2 80960cf pqfp pinout (80960cf-33, -25, -16 only) ............................................................ 16 3.4 package thermal specifications ...................................................................................................... 19 3.5 stepping register information .......................................................................................................... 22 3.6 sources for accessories ................................................................................................................... 22 4.0 electrical specifications ............................................................................................................ 23 4.1 absolute maximum ratings .............................................................................................................. 23 4.2 operating conditions ........................................................................................................................ 23 4.3 recommended connections ............................................................................................................ 24 4.4 dc specifications ............................................................................................................................. 24 4.5 ac specifications .............................................................................................................................. 26 4.5.1 ac test conditions ........................................................................................................ 36 4.5.2 ac timing waveforms .................................................................................................... 37 4.5.3 derating curves ............................................................................................................. 41 5.0 reset, backoff and hold acknowledge ................................................................................ 42 6.0 bus waveforms .................................................................................................................................. 44 7.0 revision history ............................................................................................................................... 71
iv preliminary contents a figures figure 1. 80960cf block diagram ............................................................................................................ 2 figure 2. 80960cf pga pinoutview from top (pins facing down) .................................................... 12 figure 3. 80960cf pga pinout view from bottom (pins facing up) ................................................. 13 figure 4. 80960cf pqfp pinouttop view (80960cf-33, -25, -16 only) ............................................ 19 figure 5. measuring 80960cf pga and pqfp case temperature ....................................................... 20 figure 6. register g0 ............................................................................................................................... 22 figure 7. ac test load ........................................................................................................................... 37 figure 8. input and output clocks waveform ......................................................................................... 37 figure 9. clkin waveform ..................................................................................................................... 37 figure 10. output delay and float waveform ........................................................................................... 38 figure 11. input setup and hold w aveform .............................................................................................. 38 figure 12. nmi , xint7:0 input setup and hold w aveform ....................................................................... 39 figure 13. hold acknowledge timings ...................................................................................................... 39 figure 14. bus backoff (boff) timings ................................................................................................... 40 figure 15. relative timings waveforms ................................................................................................... 40 figure 16. output delay or hold vs. load capacitance ............................................................................ 41 figure 17. rise and fall time derating at highest operating temperature and minimum v cc ............... 41 figure 18. i cc vs. frequency and temperature80960cf-33, -25, -16 .................................................. 42 figure 19. i cc vs. frequency and temperature80960cf-40 ................................................................ 42 figure 20. cold reset waveform .............................................................................................................. 44 figure 21. warm reset waveform ............................................................................................................ 45 figure 22. entering the once state ......................................................................................................... 46 figure 23. clock synchronization in the 2-x clock mode .......................................................................... 47 figure 24. clock synchronization in the 1-x clock mode .......................................................................... 47 figure 25. non-burst, non-pipelined requests without wait states ........................................................ 48 figure 26. non-burst, non-pipelined read request with wait states ..................................................... 49 figure 27. non-burst, non-pipelined write request with wait states ..................................................... 50 figure 28. burst, non-pipelined read request without wait states, 32-bit bus ..................................... 51 figure 29. burst, non-pipelined read request with wait states, 32-bit bus .......................................... 52 figure 30. burst, non-pipelined write request without wait states, 32- bit bus ..................................... 53 figure 31. burst, non-pipelined write request with wait states, 32-bit bus .......................................... 54 figure 32. burst, non-pipelined read request with wait states, 16-bit bus .......................................... 55 figure 33. burst, non-pipelined read request with wait states, 8-bit bus ............................................ 56 figure 34. non-burst, pipelined read request without wait states, 32-bit bus ..................................... 57 figure 35. non-burst, pipelined read request with wait states, 32-bit bus .......................................... 58 figure 36. burst, pipelined read request without wait states, 32-bit bus ............................................. 59 figure 37. burst, pipelined read request with wait states, 32-bit bus .................................................. 60 figure 38. burst, pipelined read request with wait states, 16-bit bus .................................................. 61 figure 39. burst, pipelined read request with wait states, 8-bit bus .................................................... 62
preliminary v a contents figure 40. using external ready ............................................................................................................ 63 figure 41. terminating a burst with bterm ............................................................................................. 64 figure 42. boff functional timing .......................................................................................................... 65 figure 43. hold functional timing .......................................................................................................... 66 figure 44. dreq and dack functional timing ....................................................................................... 67 figure 45. eop functional timing ............................................................................................................ 67 figure 46. terminal count functional timing ........................................................................................... 68 figure 47. fail functional timing ............................................................................................................ 68 figure 48. a summary of aligned and unaligned transfers for little endian regions ............................. 69 figure 49. a summary of aligned and unaligned transfers for little endian regions (continued) ......... 70 figure 50. idle bus operation ................................................................................................................... 71 tables table 1. 80960cf instruction set ............................................................................................................ 4 table 2. 80960cf pin description external bus signals .................................................................... 6 table 3. 80960cf pin description processor control signals ............................................................ 9 table 4. 80960cf pin description dma and interrupt unit control signals ..................................... 11 table 5. 80960cf pga pinout in signal order ................................................................................ 14 table 6. 80960cf pga pinout in pin order ..................................................................................... 15 table 7. 80960cf pqfp pinout in signal order (80960cf-33, -25, -16 only) ................................ 17 table 8. 80960cf pqfp pinout in pin order (80960cf-33, -25, -16 only) ..................................... 18 table 9. maximum t a at various airflows in o c (pga package only) ................................................... 20 table 10. 80960cf pga package thermal characteristics ................................................................... 21 table 11. 80960cf pqfp package thermal characteristics ................................................................. 21 table 12. die stepping cross reference ................................................................................................ 22 table 13. operating conditions ............................................................................................................... 23 table 14. dc characteristics ................................................................................................................... 24 table 15. 80960cf ac characteristics (40 mhz) ................................................................................... 26 table 16. 80960cf ac characteristics (33 mhz) ................................................................................... 29 table 17. 80960cf ac characteristics (25 mhz) ................................................................................... 32 table 18. 80960cf ac characteristics (16 mhz) ................................................................................... 34 table 19. reset conditions ..................................................................................................................... 43 table 20. hold acknowledge and backoff conditions ............................................................................. 43

a 80960cf-40, -33, -25, -16 preliminary 1 1.0 purpose this document provides electrical characteristics of intels i960 ? cf embedded microprocessor. for functional descriptions consult the i960 ? cx micro- processor users manual (270710). to obtain data sheet updates and errata, contact intel at any of the following numbers. 2.0 80960cf overview intels 80960cf is the second processor in the series of superscalar i960 microprocessors that also includes the 80960ca and the 80960ha/hd/ht. upgrading from the 80960ca to the 80960cf is straightforward because the two processors are socket- and object code-compatible. as shown in figure 1, the 80960cfs instruction cache is 4 kbytes; data cache is 1 kbyte (80960ca instruction cache is 1 kbyte; it does not have a data cache.) this extra cache on the cf adds a signifi- cant performance boost over the ca. intels world-wide web (www) location: http://www.intel.com/ customer support (us and canada): 800-628-8686 faxback service: us and canada 800-628-2283 europe +44(0)793-496646 worldwide 916-356-3105 application bulletin board service: up to 14.4-kbaud line, worldwide 916-356-3600 dedicated 2400-baud line, worldwide 916-356-7209 europe +44(0)793-496340
2 preliminary 80960cf-40, -33, -25, -16 a figure 1. 80960cf block diagram execution unit programmable bus controller bus request queues six-port register file 64-bit src1 bus 64-bit src2 bus 64-bit dst bus 32-bit base bus 128-bit load bus 128-bit store bus instruction instruction cache (4 kbyte, two-way set associative) 128-bit cache bus prefetch queue interrupt controller control address data memory-side machine bus register-side machine bus parallel instruction scheduler memory region configuration multiply/divide unit four-channel dma controller interrupt port 1 kbyte 5 to 15 sets register cache data ram address generation unit f_cf001a dma port 1 kbyte direct mapped data cache the 80960cf, object code compatible with the 32-bit 80960 core architecture, employs special function register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware. multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions per clock with peak execution of three instructions per clock. a 32-bit demultiplexed and pipelined burst bus provides a 132 mbyte/s bandwidth to a systems high-speed external memory subsystem. also, the 80960cfs on-chip caching of instructions, proce- dure context and critical program data substantially decouples system performance from the wait states associated with accesses to the systems slower, cost sensitive, main memory subsystem. the 80960cf bus controller integrates full wait state and bus width control for highest system perfor- mance with minimal system design complexity. unaligned access and big endian byte order support reduces the cost of porting existing applications to the 80960cf.
a 80960cf-40, -33, -25, -16 preliminary 3 the processor also integrates four complete data- chaining dma channels and a high-speed interrupt controller on-chip. dma channels perform single- cycle or two-cycle transfers, data packing and unpacking and data chaining. block transfers in addition to source or destination synchronized trans- fers are supported. the interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (latency) time of 625 ns. 2.1 the 80960c-series core the c-series core is a very high performance microarchitectural implementation of the 80960 core architecture. this core can sustain execution of two instructions per clock (80 mips at 40 mhz). to achieve this level of performance, intel has incorpo- rated state-of-the-art silicon technology and innova- tive microarchitectural constructs into the c-series core implementation. factors that contribute to the cores performance include: ? parallel instruction decoding allows issuance of up to three instructions per clock ? single-clock execution of most instructions ? parallel instruction decode allows sustained, simultaneous execution of two single-clock instruc- tions every clock cycle ? efficient instruction pipeline minimizes pipeline break losses ? register and resource scoreboarding allow simul- taneous multi-clock instruction execution ? branch look-ahead and prediction allows many branches to execute with no pipeline break ? local register cache integrated on-chip caches call/return context ? two-way set associative, 4 kbyte integrated instruction cache ? 1 kbyte integrated data ram sustains a four-word (128-bit) access every clock cycle ? direct mapped, 1 kbyte data cache, write through, write allocate 2.2 pipelined, burst bus a 32-bit high performance bus controller interfaces the 80960cf to external memory and peripherals. the bus control unit features a maximum transfer rate of 160 mbytes per second (at 40 mhz). inter- nally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. the bus control units main features include: ? demultiplexed, burst bus to exploit most efficient dram access modes ? address pipelining to reduce memory cost while maintaining performance ? 32-, 16- and 8-bit modes for i/o interfacing ease ? full internal wait state generation to reduce system cost ? little and big endian support to ease application development ? unaligned access support for code portability ? three-deep request queue to decouple the bus from the core 2.3 instruction set summary table 1 summarizes the 80960cf instruction set by logical groupings. see the i960 ? cx microprocessor users manual (270710) for a complete description of the instruction set. 2.4 flexible dma controller a four-channel dma controller provides high speed dma control for data transfers involving peripherals and memory. the dma provides advanced features such as data chaining, byte assembly and disas- sembly and a high performance fly-by mode capable of transfer speeds of up to 71 mbytes per second at 40 mhz. the dma controller features a performance and flexibility which is only possible by integrating the dma controller and the 80960cf core.
80960cf-40, -33, -25, -16 a 4 preliminary 2.5 priority interrupt controller a programmable-priority interrupt controller manages up to 248 external sources through the 8- bit external interrupt port. the interrupt unit also handles the four internal sources from the dma controller and a single non-maskable interrupt input. the 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. 80960cf interrupts are prioritized and signaled within 225 ns of the request. if the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically completes in another 400 ns. the interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications. table 1. 80960cf instruction set data movement arithmetic logical bit / bit field / byte load store move load address add subtract multiply divide remainder modulo shift *extended shift extended multiply extended divide add with carry subtract with carry rotate and not and and not or exclusive or not or or not nor exclusive nor not nand set bit clear bit not bit alter bit scan for bit span over bit extract modify scan byte for equal comparison branch call/return fault compare conditional compare compare and increment compare and decrement test condition code check bit unconditional branch conditional branch compare and branch call call extended call system return branch and link conditional fault synchronize faults debug processor mgmt atomic modify trace controls mark force mark flush local registers modify arithmetic controls modify process controls *system control *dma control atomic add atomic modify notes: instructions marked by (*) are 80960cx extensions to the 80960 instruction set.
a 80960cf-40, -33, -25, -16 preliminary 5 3.0 package information 3.1 package introduction this section describes the pins, pinouts and thermal characteristics for the 80960cf in the 168-pin ceramic pin grid array (pga) package; the 80960cf-33, -25, -16 devices are also available in the 196-pin plastic quad flat package (pqfp). for complete package specifications and information, see the packaging handbook (# 240800). 3.2 pin descriptions this section defines the 80960cf pins. table 2 presents the legend for interpreting the pin descrip- tions in the following tables. pins associated with the 32-bit demultiplexed processor bus are described in table 2. pins associated with the 80960cf dma controller and interrupt unit are described in table 3. pins associated with basic processor configuration and control are described in table 2. all pins float while the processor is in the once mode. symbol description i input only pin o output only pin i/o pin can be either an input or output C pins must be connected as described s(...) synchronous. inputs must meet setup and hold times relative to pclk2:1 for proper operation. outputs are synchro- nous to pclk2:1. s(e) edge sensitive input s(l) level sensitive input a(...) asynchronous. inputs may be asynchro- nous to pclk2:1. a(e) edge sensitive input a(l) level sensitive input h(...) while the bus is in the hold acknowledge or bus backoff state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) continues to be a valid input r(...) while the processors reset pin is low, the pin: r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(q) continues to be a valid output
6 preliminary 80960cf-40, -33, -25, -16 a table 2. 80960cf pin description external bus signals (sheet 1 of 3) name type description a31:2 o s h(z) r(z) address bus carries the physical address upper 30 bits. a31 is the most significant bit; a2 is least significant. during a bus access, a31:2 identify all external addresses to word (4-byte) boundaries. byte enable signals indicate the selected byte in each word. during burst accesses, a3:2 increment to indicate successive data cycles. d31:0 i/o s(l) h(z) r(z) data bus carries 32-, 16- or 8-bit data quantities depending on bus width configura- tion. the least significant bit is carried on d0 and the most significant on d31. when the bus is configured for 8-bit data, the lower 8 data lines, d7:0 are used. for 16-bit data bus widths, d15:0 are used. for 32-bit bus widths the full data bus is used. be3:0 o s h(z) r(1) byte enables select which of the four bytes addressed by a31:2 are active during an access to a memory region configured for a 32-bit data-bus width. be3 applies to d31:24; be2 applies to d23:16; be1 applies to d15:8 be0 applies to d7:0. 32-bit bus: be3 byte enable 3 enable d31:24 be2 byte enable 2 enable d23:16 be1 byte enable 1 enable d15:8 be0 byte enable 0 enable d7:0 for accesses to a memory region configured for a 16-bit data-bus width, the processor uses the be3 , be1 and be0 pins as bhe , a1 and ble respectively. 16-bit bus: be3 byte high enable (bhe ) enable d15:8 be2 not used (driven high or low) be1 address bit 1 (a1) be0 byte low enable (ble ) enable d7:0 for accesses to a memory region configured for an 8-bit data-bus width, the processor uses the be1 and be0 pins as a1 and a0 respectively. 8-bit bus: be3 not used (driven high or low) be2 not used (driven high or low) be1 address bit 1 (a1) be0 address bit 0 (a0) w/r o s h(z) r(0) write/read is asserted for read requests and deasserted for write requests. the w/r signal changes in the same clock cycle as ads . it remains valid for the entire access in non-pipelined regions. in pipelined regions, w/r is not guaranteed to be valid in the last cycle of a read access. ads o s h(z) r(1) address strobe indicates a valid address and the start of a new bus access. ads is asserted for the first clock of a bus access. ready i s(l) h(z) r(z) ready is an input which signals the termination of a data transfer. ready is used to indicate that read data on the bus is valid or that a write-data transfer has completed. the ready signal works in conjunction with the internally programmed wait-state generator. if ready is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. if the ready pin is deasserted, wait states continue to be inserted until ready becomes asserted. this is true for the n rad , n rdd , n wad and n wdd wait states. the n xda wait states cannot be extended.
preliminary 7 a 80960cf-40, -33, -25, -16 bterm i s(l) h(z) r(z) burst terminate is an input which breaks up a burst access and causes another address cycle to occur. the bterm signal works in conjunction with the internally programmed wait-state generator. if ready and bterm are enabled in a region, the bterm pin is sampled after the programmed number of wait states has expired. when bterm is asserted, a new ads signal is generated and the access is completed. the ready input is ignored when bterm is asserted. bterm must be externally synchro- nized to satisfy bterm setup and hold times. wait o s h(z) r(1) wait indicates internal wait state generator status. wait is asserted when wait states are being caused by the internal wait state generator and not by the ready or bterm inputs. wait can be used to derive a write-data strobe. wait can also be thought of as a ready output that the processor provides when it is inserting wait states. blast o s h(z) r(0) burst last indicates the last transfer in a bus access. blast is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. blast remains asserted until the clock following the last cycle of the last data transfer of a bus access. if the ready or bterm input is used to extend wait states, the blast signal remains asserted until ready or bterm terminates the access. dt/r o s h(z) r(0) data transmit/receive indicates direction for data transceivers. dt/r is used in conjunction with den to provide control for data transceivers attached to the external bus. when dt/r is asserted, the signal indicates that the processor receives data. conversely, when deasserted, the processor sends data. dt/r changes only while den is high. den o s h(z) r(1) data enable indicates data cycles in a bus request. den is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. den is used in conjunction with dt/r to provide control for data transceivers attached to the external bus. den remains asserted for sequential reads from pipelined memory regions. den is deasserted when dt/r changes. lock o s h(z) r(1) bus lock indicates that an atomic read-modify-write operation is in progress. lock may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. lock is asserted in the first clock of an atomic opera- tion and deasserted in the clock cycle following the last bus access for the atomic operation. to allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when lock is asserted. the processor performs dma transfers while lock is active. hold i s(l) h(z) r(z) hold request signals that an external agent requests access to the external bus. the processor asserts holda after completing the current bus request. hold, holda and breq are used together to arbitrate access to the processors external bus by external bus agents. boff i s(l) h(z) r(z) bus backoff , when asserted, suspends the current access and causes the bus pins to float. when boff is deasserted, the ads signal is asserted on the next clock cycle and the access is resumed. table 2. 80960cf pin description external bus signals (sheet 2 of 3) name type description
8 preliminary 80960cf-40, -33, -25, -16 a holda o s h(1) r(q) hold acknowledge indicates to a bus requestor that the processor has relin- quished control of the external bus. when holda is asserted, the external address bus, data bus and bus control signals are floated. hold, boff , holda and breq are used together to arbitrate access to the processors external bus by external bus agents. since the processor grants hold requests and enters the hold acknowledge state even while reset is asserted, the state of the holda pin is independent of the reset pin. breq o s h(q) r(0) bus request is asserted when the bus controller has a request pending. breq can be used by external bus arbitration logic in conjunction with hold and holda to deter- mine when to return mastership of the external bus to the processor. d/c o s h(z) r(z) data or code is asserted for a data request and deasserted for instruction requests. d/c has the same timing as w/r . dma o s h(z) r(z) dma access indicates whether the bus request was initiated by the dma controller. dma is asserted for any dma request. dma is deasserted for all other requests. sup o s h(z) r(z) supervisor access indicates whether the bus request is issued while in super- visor mode. sup is asserted when the request has supervisor privileges and is deasserted otherwise. sup can be used to isolate supervisor code and data structures from non-supervisor requests. table 2. 80960cf pin description external bus signals (sheet 3 of 3) name type description
preliminary 9 a 80960cf-40, -33, -25, -16 table 3. 80960cf pin description processor control signals (sheet 1 of 2) name type description reset i a(l) h(z) r(z) reset causes the chip to reset. when reset is asserted, all external signals return to the reset state. when reset is deasserted, initialization begins. when the 2-x clock mode is selected, reset must remain asserted for 32 clkin cycles before being deasserted to guarantee correct processor initialization. when the 1-x clock mode is selected, reset must remain asserted for 10,000 clkin cycles before being deasserted to guarantee correct processor initialization. the clkmode pin selects 1-x or 2-x input clock division of the clkin pin. the hold acknowledge bus state functions while the chip is reset. if the bus is in the hold acknowledge state when reset is asserted, the processor internally resets, but maintains the hold acknowledge state on external pins until the hold request is removed. if a hold request is made while the processor is in the reset state, the processor bus grants holda and enters the hold acknowledge state. fail o s h(q) r(0) fail indicates failure of the self-test performed at initialization. when reset is deasserted and initialization begins, the fail pin is asserted. an internal self-test is performed as part of the initialization process. if this self-test passes, the fail pin is deasserted; otherwise it remains asserted. the fail pin is reasserted while the processor performs an external bus self-confidence test. if this self-test passes, the processor deasserts the fail pin and branches to the users initialization routine; otherwise the fail pin remains asserted. internal self-test and the use of the fail pin can be disabled with the stest pin. stest i s(l) h(z) r(z) self test enables or disables the internal self-test feature at initialization. stest is read on the rising edge of reset . when asserted, internal self-test and external bus confidence tests are performed during processor initialization. when deasserted, only the bus confidence tests are performed during initialization. once i a(l) h(z) r(z) on circuit emulation , when asserted, causes all outputs to be floated. once is continuously sampled while reset is low and is latched on the rising edge of reset . to place the processor in the once state: (1) assert reset and once (order does not matter) (2) wait for at least 16 clkin periods in 2-x modeor 10,000 clkin periods in 1-x modeafter v cc and clkin are within operating specifications (3) deassert reset (4) wait at least 32 clkin periods (the processor will now be latched in the once state while reset is high.) to exit the once state, bring v cc and clkin to operating conditions, then assert reset and bring once high prior to deasserting reset . clkin must operate within the specified operating conditions until step 4 completes. clkin may then be changed to dc to achieve the lowest possible once mode leakage current. once can be used by emulator products or board testers to effectively make an installed processor transparent in the board.
10 preliminary 80960cf-40, -33, -25, -16 a clkin i a(e) h(z) r(z) clock input is an input for the external clock needed to run the processor. the external clock is internally divided as prescribed by the clkmode pin to produce pclk2:1. clkmode i a(l) h(z) r(z) clock mode selects the division factor applied to the external clock input (clkin). when clkmode is high, clkin is divided by one to create pclk2:1 and the processors internal clock. when clkmode is low, clkin is divided by two to create pclk2:1 and the processors internal clock. clkmode should be tied high or low in a system as the clock mode is not latched by the processor. if left unconnected, the processor internally pulls the clkmode pin low, enabling the 2-x clock mode. pclk2:1 o s h(q) r(q) processor output clocks provide a timing reference for all inputs and outputs. all input and output timings are specified in relation to pclk2 and pclk1. pclk2 and pclk1 are identical signals. two output pins are provided to allow flexi- bility in the systems allocation of capacitive loading on the clock. pclk2:1 may also be connected at the processor to form a single clock signal. v ss C ground connections must be connected externally to a v ss board plane. v cc C power connections must be connected externally to a v cc board plane. v ccpll C v ccpll is a separate v cc supply pin for the phase lock loop used in 1-x clock mode. connecting a simple lowpass filter to v ccpll may help reduce clock jitter (t cp ) in noisy environments. otherwise, v ccpll should be connected to v cc . nc C no connect pins must not be connected in a system. table 3. 80960cf pin description processor control signals (sheet 2 of 2) name type description
preliminary 11 a 80960cf-40, -33, -25, -16 table 4. 80960cf pin description dma and interrupt unit control signals name type description dreq3:0 i a(l) h(z) r(z) dma request is used to request a dma transfer. each of the four signals requests a transfer on a single channel. dreq0 requests channel 0, dreq1 requests channel 1, etc. when two or more channels are requested simultaneously, the channel with the highest priority is serviced first. channel priority mode is programmable. dack3:0 o s h(1) r(1) dma acknowledge indicates that a dma transfer is being executed. each of the four signals acknowledges a transfer for a single channel. dack0 acknowl- edges channel 0, dack1 acknowledges channel 1, etc. dack3:0 are asserted when the requesting device of a dma is accessed. eop /tc3:0 i/o a(l) h(z/q) r(z) end of process/terminal count can be programmed as either an input (eop3:0 ) or output (tc3:0 ), but not both. each pin is individually programmable. when programmed as an input, eopx causes termination of a current dma transfer for the channel that corresponds to the eopx pin. eop0 corresponds to channel 0, eop1 corresponds to channel 1, etc. when a channel is configured for source and destination chaining, the eop pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. eop3:0 are asynchronous inputs. when programmed as an output, the channels tcx pin indicates that the channel byte count has reached 0 and a dma has terminated. tcx is driven with the same timing as dackx during the last dma transfer for a buffer. if the last bus request is executed as multiple bus accesses, tcx stays asserted for the entire bus request. xint7:0 i a(e/l) h(z) r(z) external interrupt pins cause interrupts to be requested. these pins can be configured in three modes: dedicated mode: each pin is a dedicated external interrupt source. dedicated inputs can be individually programmed to be level (low) or edge (falling) activated. expanded mode: the eight pins act together as an 8-bit vectored interrupt source. the interrupt pins in this mode are level activated. since the interrupt pins are active low, the vector number requested is the 1s complement of the positive logic value place on the port. this eliminates glue logic to interface to combinational priority encoders which output negative logic. mixed mode: xint7:5 are dedicated sources and xint4:0 act as the five most significant bits of an expanded mode vector. the least significant bits are set to 010 internally. nmi i a(e) h(z) r(z) non-maskable interrupt causes a non-maskable interrupt event to occur. nmi is the highest priority interrupt recognized. nmi is an edge (falling) activated source.
80960cf-40, -33, -25, -16 a 12 preliminary 3.3 80960cf mechanical data 3.3.1 80960cf pga pinout figure 2 depicts the complete 80960cf pga pinout as viewed from the top side of the component (i.e., pins facing down). figure 3 shows the complete 80960cf pga pinout as viewed from the pin-side of the package (i.e., pins facing up). table 5 lists the 80960cf pin names and package location in signal order; table 6 lists the pin names and package location in pin order. see section 4.0, electrical specifications for specifications and recommended connections. figure 2. 80960cf pga pinoutview from top (pins facing down) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w/r v ss v cc dt/r a29 lock sup wait dma a28 a30 breq d/ c d3 d1 once nc nc v cc v ss v ss v ss v ss v ss clkin clkmode v ss boff stest nc nc dreq0 dreq2 v cc dack0 v cc v ccpll v cc pclk2 pclk1 v cc nc fail nc nc nc dreq1 dreq3 dack1 dack2 dack3 eop /tc0 eop /tc2 eop /tc3 eop /tc1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a b c d e f g h j k l m n p q r s f_ca002a a b c d e f g h j k l m n p q r s
preliminary 13 a 80960cf-40, -33, -25, -16 figure 3. 80960cf pga pinout view from bottom (pins facing up) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w/r v ss v cc dt/r a29 lock sup wait dma a28 a30 breq d/c d3 d1 once nc nc v cc v ss v ss v ss v ss v ss clkin clk mode v ss boff stest nc nc dreq0 dreq2 v cc dack0 v cc v ccpll v cc pclk2 pclk1 v cc nc fail nc nc nc dreq1 dreq3 dack1 dack2 dack3 eop /tc0 eop /tc2 eop /tc3 eop /tc1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 f_ca003a a bcdefghjklmnpqrs a bcdefghjklmnpqrs metal lid
14 preliminary 80960cf-40, -33, -25, -16 a table 5. 80960cf pga pinout in signal order address bus data bus bus control processor control i/o signal pin signal pin signal pin signal pin signal pin a31 s15 d31 r3 be3 s5 reset a16 dreq3 a7 a30 q13 d30 q5 be2 s6 dreq2 b6 a29 r14 d29 s2 be1 s7 fail a2 dreq1 a6 a28 q14 d28 q4 be0 r9 dreq0 b5 a27 s16 d27 r2 stest b2 a26 r15 d26 q3 w/r s10 dack3 a10 a25 s17 d25 s1 once c3 dack2 a9 a24 q15 d24 r1 ads r6 dack1 a8 a23 r16 d23 q2 clkin c13 dack0 b8 a22 r17 d22 p3 ready s3 clkmode c14 a21 q16 d21 q1 bterm r4 plck1 b14 eop /tc3 a14 a20 p15 d20 p2 plck2 b13 eop /tc2 a13 a19 p16 d19 p1 wait s12 eop /tc1 a12 a18 q17 d18 n2 blast s8 v ss eop /tc0 a11 a17 p17 d17 n1 location a16 n16 d16 m1 dt/r s11 c7, c8, c9, c10, c11, c12, f15, g3, g15, h3, h15, j3, j15, k3, k15, l3, l15, m3, m15, q7, q8, q9, q10, q11 xint7 c17 a15 n17 d15 l1 den s9 xint6 c16 a14 m17 d14 l2 xint5 b17 a13 l16 d13 k1 lock s14 xint4 c15 a12 l17 d12 j1 xint3 b16 a11 k17 d11 h1 v cc xint2 a17 a10 j17 d10 h2 hold r5 location xint1 a15 a9 h17 d9 g1 holda s4 b7, b9, b11, b12, c6, e15, f3, f16, g2, h16, j2, j16, k2, k16, m2, m16, n3, n15, q6, r7, r8, r10, r11 xint0 b15 a8 g17 d8 f1 breq r13 a7 g16 d7 e1 nmi d15 a6 f17 d6 f2 d/c s13 a5 e17 d5 d1 dma r12 a4 e16 d4 e2 sup q12 v ccpll b10 a3 d17 d3 c1 no connect a2 d16 d2 d2 boff b1 location d1 c2 a1, a3, a4, a5, b3, b4, c4, c5, d3 d0 e3
preliminary 15 a 80960cf-40, -33, -25, -16 table 6. 80960cf pga pinout in pin order pin signal pin signal pin signal pin signal pin signal a1 nc c1 d3 f17 a6 m15 v ss r3 d31 a2 fail c2 d1 g1 d9 m16 v cc r4 bterm a3 nc c3 once g2 v cc m17 a14 r5 hold a4 nc c4 nc g3 v ss n1 d17 r6 ads a5 nc c5 nc g15 v ss n2 d18 r7 v cc a6 dreq1 c6 v cc g16 a7 n3 v cc r8 v cc a7 dreq3 c7 v ss g17 a8 n15 v cc r9 be0 a8 dack1 c8 v ss h1 d11 n16 a16 r10 v cc a9 dack2 c9 v ss h2 d10 n17 a15 r11 v cc a10 dack3 c10 v ss h3 v ss p1 d19 r12 dma a11 eop /tc0 c11 v ss h15 v ss p2 d20 r13 breq a12 eop/tc1 c12 v ss h16 v cc p3 d22 r14 a29 a13 eop/tc2 c13 clkin h17 a9 p15 a20 r15 a26 a14 eop/tc3 c14 clkmode j1 d12 p16 a19 r16 a23 a15 xint1 c15 xint4 j2 v cc p17 a17 r17 a22 a16 reset c16 xint6 j3 v ss q1 d21 s1 d25 a17 xint2 c17 xint7 j15 v ss q2 d23 s2 d29 b1 boff d1 d5 j16 v cc q3 d26 s3 ready b2 stest d2 d2 j17 a10 q4 d28 s4 holda b3 nc d3 nc k1 d13 q5 d30 s5 be3 b4 nc d15 nmi k2 v cc q6 v cc s6 be2 b5 dreq0 d16 a2 k3 v ss q7 v ss s7 be1 b6 dreq2 d17 a3 k15 v ss q8 v ss s8 blast b7 v cc e1 d7 k16 v cc q9 v ss s9 den b8 dack0 e2 d4 k17 a11 q10 v ss s10 w/r b9 v cc e3 d0 l1 d15 q11 v ss s11 dt/r b10 v ccpll e15 v cc l2 d14 q12 sup s12 wait b11 v cc e16 a4 l3 v ss q13 a30 s13 d/c b12 v cc e17 a5 l15 v ss q14 a28 s14 lock b13 pclk2 f1 d8 l16 a13 q15 a24 s15 a31 b14 pclk1 f2 d6 l17 a12 q16 a21 s16 a27 b15 xint0 f3 v cc m1 d16 q17 a18 s17 a25 b16 xint3 f15 v ss m2 v cc r1 d24 b17 xint5 f16 v cc m3 v ss r2 d27
16 preliminary 80960cf-40, -33, -25, -16 a 3.3.2 80960cf pqfp pinout (80960cf-33, -25, -16 only) tables 7 and 8 list the 80960cf pin names with package location. figure 4 shows the 80960cf pqfp pinout as viewed from the top side. see section 4.0, electrical specifications for specifications and recom- mended connections.
preliminary 17 a 80960cf-40, -33, -25, -16 table 7. 80960cf pqfp pinout in signal order (80960cf-33, -25, -16 only) address bus data bus bus control processor control i/o signal pin signal pin signal pin signal pin signal pin a31 153 d31 186 be3 176 reset 91 dreq3 60 a30 152 d30 187 be2 175 fail 45 dreq2 59 a29 151 d29 188 be1 172 stest 46 dreq1 58 a28 145 d28 189 be0 170 once 43 dreq0 57 a27 144 d27 191 clkin 87 a26 143 d26 192 w/r 164 clkmode 85 dack3 65 a25 142 d25 194 pclk2 74 dack2 64 a24 141 d24 195 ads 178 pclk1 78 dack1 63 a23 139 d23 3 v ss dack0 62 a22 138 d22 4 ready 182 location a21 137 d21 5 bterm 184 2, 7, 16, 24, 30, 38, 39, 49, 56, 70, 75, 77, 81, 83, 88, 89, 92, 98, 105, 109, 110, 121, 125, 131, 135, 147, 150, 161, 165, 173, 174, 185, 196 eop/tc3 69 a20 136 d20 6 eop/tc2 68 a19 134 d19 8 wait 162 eop/tc1 67 a18 133 d18 9 blast 169 eop/tc0 66 a17 132 d17 10 a16 130 d16 11 dt/r 163 xint7 107 a15 129 d15 13 den 167 v cc xint6 106 a14 128 d14 14 location xint5 102 a13 124 d13 15 lock 156 1, 12, 20, 28, 32, 37, 44, 50, 61, 71, 79, 82, 96, 99, 103, 115, 127, 140, 148, 154, 168, 171, 180, 190 xint4 101 a12 123 d12 17 xint3 100 a11 122 d11 18 hold 181 xint2 95 a10 120 d10 19 holda 179 xint1 94 a9 119 d9 21 breq 155 xint0 93 a8 118 d8 22 v ccpll 72 a7 117 d7 23 d/c 159 no connect nmi 108 a6 116 d6 25 dma 160 location a5 114 d5 26 sup 158 29, 31, 41, 42, 47, 48, 51, 52, 53, 54, 55, 73, 76, 80, 84, 86, 90, 97, 104, 126, 146, 149, 157, 166, 177, 183, 193 a4 113 d4 27 a3 112 d3 33 boff 40 a2 111 d2 34 d1 35 d0 36
18 preliminary 80960cf-40, -33, -25, -16 a table 8. 80960cf pqfp pinout in pin order (80960cf-33, -25, -16 only) pin signal pin signal pin signal pin signal pin signal pin signal 1v cc 34 d2 67 eop / tc1 100 xint3 133 a18 166 nc 2v ss 35 d1 68 eop / tc2 101 xint4 134 a19 167 den 3 d23 36 d0 69 eop / tc3 102 xint5 135 v ss 168 v cc 4 d22 37 v cc 70 v ss 103 v cc 136 a20 169 blast 5 d21 38 v ss 71 v cc 104 nc 137 a21 170 be0 6 d20 39 v ss 72 v ccpll 105 v ss 138 a22 171 v cc 7v ss 40 boff 73 nc 106 xint6 139 a23 172 be1 8 d19 41 nc 74 pclk2 107 xint7 140 v cc 173 v ss 9 d18 42 nc 75 v ss 108 nmi 141 a24 174 v ss 10 d17 43 once 76 nc 109 v ss 142 a25 175 be2 11 d16 44 v cc 77 v ss 110 v ss 143 a26 176 be3 12 v cc 45 fail 78 pclk1 111 a2 144 a27 177 nc 13 d15 46 stest 79 v cc 112 a3 145 a28 178 ads 14 d14 47 nc 80 nc 113 a4 146 nc 179 holda 15 d13 48 nc 81 v ss 114 a5 147 v ss 180 v cc 16 v ss 49 v ss 82 v cc 115 v cc 148 v cc 181 hold 17 d12 50 v cc 83 v ss 116 a6 149 nc 182 ready 18 d11 51 nc 84 nc 117 a7 150 v ss 183 nc 19 d10 52 nc 85 clkmode 118 a8 151 a29 184 bterm 20 v cc 53 nc 86 nc 119 a9 152 a30 185 v ss 21 d9 54 nc 87 clkin 120 a10 153 a31 186 d31 22 d8 55 nc 88 v ss 121 v ss 154 v cc 187 d30 23 d7 56 v ss 89 v ss 122 a11 155 breq 188 d29 24 v ss 57 dreq0 90 nc 123 a12 156 lock 189 d28 25 d6 58 dreq1 91 reset 124 a13 157 nc 190 v cc 26 d5 59 dreq2 92 v ss 125 v ss 158 sup 191 d27 27 d4 60 dreq3 93 xint0 126 nc 159 d/ c 192 d26 28 v cc 61 v cc 94 xint1 127 v cc 160 dma 193 nc 29 nc 62 dack0 95 xint2 128 a14 161 v ss 194 d25 30 v ss 63 dack1 96 v cc 129 a15 162 wait 195 d24 31 nc 64 dack2 97 nc 130 a16 163 dt/ r 196 v ss 32 v cc 65 dack3 98 v ss 131 v ss 164 w/ r 33 d3 66 eop / tc0 99 v cc 132 a17 165 v ss
preliminary 19 a 80960cf-40, -33, -25, -16 figure 4. 80960cf pqfp pinouttop view (80960cf-33, -25, -16 only) 50 98 99 147 148 196 pin 1 49 f_ca004a 3.4 package thermal specifications the 80960cf is specified for operation when t c (case temperature) is within the range of 0cC100c for 33, 25, and 16 mhz and 0cC85c for 40 mhz. t c may be measured in any environment to deter- mine whether the 80960cf is within specified oper- ating range. case temperature should be measured at the center of the top surface, opposite the pins. refer to figure 5. t a (ambient temperature) is calculated from q ca (thermal resistance from case to ambient) using the equation: t a = t c C p* q ca table 9 shows the maximum t a allowable (without exceeding t c ) at various airflows and operating frequencies (f pclk ). note that t a is greatly improved by attaching fins or a heatsink to the package. p (maximum power consumption) is calculated by using the typical i cc as tabulated in section 4.4, dc specifications and v cc of 5 v.
20 preliminary 80960cf-40, -33, -25, -16 a figure 5. measuring 80960cf pga and pqfp case temperature table 9. maximum t a at various airflows in o c (pga package only) airflow-ft/min (m/sec) f pclk (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) t a with heatsink* 40 33 25 16 20 38 50 63 40 57 65 74 58 74 79 84 60 76 81 86 66 81 85 89 68 84 87 90 t a without heatsink* 40 33 25 16 0 18 34 51 15 33 46 60 30 47 57 68 40 57 65 74 50 66 72 80 52 67 74 81 notes: *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). measure pqfp case temperature at center of top surface. measure pga temperature at center of top surface 168 - pin pga pin 196 pin 1
preliminary 21 a 80960cf-40, -33, -25, -16 table 10. 80960cf pga package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.07) 800 (4.06) 1000 (5.07) q junction-to-case (case measured as shown in figure 5) 1.5 1.5 1.5 1.5 1.5 1.5 q case-to-ambient (no heatsink) 17 14 11 9 7.1 6.6 q case-to-ambient (with heatsink)* 13 9 5.5 5 3.9 3.4 notes: 1. this table applies to 80960cf pga plugged into socket or soldered directly to board. 2. q ja = q jc + q ca *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). table 11. 80960cf pqfp package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) q junction-to-case (case measured as shown in figure 5) 5555555 q case-to-ambient (no heatsink) 19 18 17 15 12 10 9 notes: 1. this table applies to 80960cf pqfp soldered directly to board. 2. q ja = q jc + q ca aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa q jc q ja q jc
80960cf-40, -33, -25, -16 a 22 preliminary 3.5 stepping register information upon reset, register g0 contains die stepping infor- mation (figure 6). the most significant byte contains ascii 0; the upper middle byte contains an ascii c; the lower middle byte contains an ascii f. the least significant byte contains the stepping number in ascii. g0 retains this information until it is over- written by the user program. table 12 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. figure 6. register g0 table 12. die stepping cross reference g0 least significant byte die stepping 01 a 02 b 03 c 04 d 05 e ascii 00 43 46 stepping number decimal 0 c f stepping number msb lsb 3.6 sources for accessories the following is a list of suggested sources for 80960cf accessories. this is neither an endorse- ment nor a warranty of the performance of any of the listed products and/or companies. sockets 1. 3m textool test and interconnection products 6801 river place blvd. mailstop 130-3n-29 austin, tx 78726-9000 (800) 328-0411 2. augat, inc. interconnection products group 452 john dietsch blvd. attleboro falls, ma 02763 (508) 699-7646 3. concept mfg., inc. (decoupling sockets) 400 walnut st. suite 609 redwood city, ca 94063 (415) 365-1162 fax: (415)265-1164 heatsinks/fins 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75234 (214) 243-4321 fax: (214) 241-4656 2. wakefield engineering 60 audubon road wakefield, ma 01880 (617) 245-5900
a 80960cf-40, -33, -25, -16 preliminary 23 4.0 electrical specifications 4.1 absolute maximum ratings parameter maximum rating storage temperature................................ C65c to +150c case temperature under bias ..................C65c to +110c supply voltage wrt. v ss ............................C0.5 v to + 6.5 v voltage on other pins wrt. v ss ......... C0.5 v to v cc + 0.5 v notice: this document contains preliminary infor- mation on new products in production.the specifi- cations are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause perma- nent damage. these are stress ratings only. opera- tion beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. 4.2 operating conditions table 13. operating conditions symbol parameter min max units notes v cc supply voltage 80960cf-40 80960cf-33 80960cf-25 80960CF-16 4.75 4.50 4.50 4.50 5.25 5.50 5.50 5.50 v f clk2x input clock frequency (2-x mode) 80960cf-40 80960cf-33 80960cf-25 80960CF-16 0 0 0 0 80 66 50 32 mhz f clk1x input clock frequency (1-x mode) 80960cf-40 80960cf-33 80960cf-25 80960CF-16 8 8 8 8 40 33 25 16 mhz (1) t c case temp under bias pga pkg. (80960cf-40) pga pkg. (80960cf-33, -25, -16 only) 196-pin pqfp (80960cf-33, -25, -16 only) 0 0 0 85 100 100 o c notes: 1. when in the 1-x input clock mode, clkin is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 mhz for proper processor operation. however, in the 1-x mode, clkin may still be stopped when the processor is in a reset condition. if clkin is stopped, the specified reset low time must be provided once clkin restarts and has stabilized.
80960cf-40, -33, -25, -16 a 24 preliminary 4.3 recommended connections power and ground connections must be made to multiple v cc and v ss (gnd) pins. every 80960cf- based circuit board should include power (v cc ) and ground (v ss ) planes for power distribution. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. pins identified as nc must not be connected in the system. liberal decoupling capacitance should be placed near the 80960cf. the processor can cause tran- sient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by short- ening the board traces between the processor and decoupling capacitors as much as possible. capaci- tors specifically designed for pga packages will offer the lowest possible inductance. for reliable operation, always connect unused inputs to an appropriate signal level. in particular, any unused interrupt (xint , nmi ), dma (dreq ), or bterm input should be connected to v cc through a pull-up resistor. pull-up resistors should be in the in the range of 20 k w for each pin tied high. if ready or hold are not used, the unused input should be connected to ground. n.c. pins must always remain unconnected. for additional information refer to the i960 ? cx microprocessor users manual (270710). 4.4 dc specifications table 14. dc characteristics (sheet 1 of 2) (80960cf-40, 33, -25, -16 under the conditions described in section 4.2, operating conditions .) symbol parameter min max units notes v il input low voltage for all pins except reset C 0.3 +0.8 v v ih input high voltage for all pins except reset 2.0 v cc + 0.3 v v ol output low voltage 0.45 v i ol = 5 ma v oh output high voltage i oh = C1 ma i oh = C 200 m a 2.4 v cc C 0.5 v v v ilr input low voltage for reset C 0.3 1.5 v v ihr input high voltage for reset 3.5 v cc + 0.3 v notes: 1. no pullup or pulldown. 2. these pins have internal pullup resistors. 3. these pins have internal pulldown resistors. 4. measured at worst case frequency, v cc and temperature, with device operating and outputs loaded to the test conditions described in section 4.5.1, ac test conditions. 5. i cc typical is not tested. 6. output capacitance is the capacitive load of a floating output. 7. clkmode pin has a pulldown resistor only when once pin is deasserted.
preliminary 25 a 80960cf-40, -33, -25, -16 i li1 input leakage current for each pin except : bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , boff , ready , hold, clkmode 15 a 0 v in v cc (1) i li2 input leakage current for: bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , boff 0 C 300 a v in = 0.45 v (2) i li3 input leakage current for: ready , hold, clkmode 0 500 a v in = 2.4 v (3,7) i lo output leakage current 15 a 0.45 v out v cc i cc supply current (80960cf-40, 33): i cc max i cc typ 1150 1000 ma ma (4) (5) i cc supply current (80960cf-25): i cc max i cc typ 950 775 ma ma (4) (5) i cc supply current (80960CF-16): i cc max i cc typ 750 575 ma (4) (5) i once once-mode supply current 80960cf-40 80960cf-33, -25, -16 225 150 ma c in input capacitance for: clkin, reset , once , ready , hold, dreq3:0 , boff , xint7:0 , nmi , bterm , clkmode 012pff c = 1 mhz c out output capacitance of each output pin 12 pf f c = 1 mhz (6) c i/o i/o pin capacitance 12 pf f c = 1 mhz table 14. dc characteristics (sheet 2 of 2) (80960cf-40, 33, -25, -16 under the conditions described in section 4.2, operating conditions .) symbol parameter min max units notes notes: 1. no pullup or pulldown. 2. these pins have internal pullup resistors. 3. these pins have internal pulldown resistors. 4. measured at worst case frequency, v cc and temperature, with device operating and outputs loaded to the test conditions described in section 4.5.1, ac test conditions. 5. i cc typical is not tested. 6. output capacitance is the capacitive load of a floating output. 7. clkmode pin has a pulldown resistor only when once pin is deasserted.
26 preliminary 80960cf-40, -33, -25, -16 a 4.5 ac specifications table 15. 80960cf ac characteristics (40 mhz) (sheet 1 of 3) (80960cf-40 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes input clock (1,9) t f clkin frequency 0 80 mhz t c clkin period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 25 12.5 125 ns ns (11) t cs clkin period stability in 1-x mode (f clk1x ) 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 5 5 62.5 ns ns (11) t cl clkin low time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 5 5 62.5 ns ns (11) t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1,8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) C 2 2 2 25 ns ns (3,12) (3) t pclk2:1 period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) t c 2t c ns ns (12) (3) t ph pclk2:1 high time (t/2) C 2 t/2 ns (12) t pl pclk2:1 low time (t/2) C 2 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) synchronous outputs (8) notes: see table 18 for all notes related to ac specifications.
preliminary 27 a 80960cf-40, -33, -25, -16 t oh t ov output valid delay, output hold t oh1 , t ov1 a31:2 t oh2 , t ov2 be3:0 t oh3 , t ov3 ads t oh4 , t ov4 w/r t oh5 , t ov5 d/c , sup , dma t oh6 , t ov6 blast , wait t oh7 , t ov7 den t oh8 , t ov8 holda, breq t oh9 , t ov9 lock t oh10 , t ov10 dack3:0 t oh11 , t ov11 d31:0 t oh12 , t ov12 dt/r t oh13 , t ov13 fail t oh14 , t ov14 eop3:0 /tc3:0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 14 16 16 16 16 16 16 16 16 16 16 t/2 + 14 14 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) (6,10) t of output float for all outputs 3 22 ns (6) synchronous inputs (1,9,10) t is input setup t is1 d31:0 t is2 boff t is3 bterm /ready t is4 hold 3 15 7 5 ns ns ns ns t ih input hold t ih1 d31:0 t ih2 boff t ih3 bterm /ready t ih4 hold 5 5 2 3 ns ns ns ns table 15. 80960cf ac characteristics (40 mhz) (sheet 2 of 3) (80960cf-40 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes notes: see table 18 for all notes related to ac specifications.
28 preliminary 80960cf-40, -33, -25, -16 a relative output timings (1,2,3,8) t avsh1 a31:2 valid to ads rising t C 4 t + 4 ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t C 6 t + 6 ns t avel1 a31:2 valid to den falling t C 4 t + 4 ns t avel2 be3:0 , w/r , sup , inst ,dma , dack3:0 valid to den falling t C 6 t + 6 ns t nlqv wait falling to output data valid 6 ns t dvnh output data valid to wait rising n*t C 6 n*t + 6 ns (4) t nlnh wait falling to wait rising n*t 4 ns (4) t nhqx output data hold after wait rising (n+1)*tC8 (n+1)*t+6 ns (5) t ehtv dt/r hold after den high t/2 C 7 ns (6) t tvel dt/r valid to den falling t/2 C 4 ns relative input timings (1,2,3) t is5 reset input setup (2-x clock mode) 6 ns (13) t ih5 reset input hold (2-x clock mode) 5 ns (13) t is6 dreq3 :0 input setup 12 ns (7) t ih6 dreq3:0 input hold 7 ns (7) t is7 xint7:0 , nmi input setup 7 ns (15) t ih7 xint7:0 , nmi input hold 3 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 + 1 ns (14) table 15. 80960cf ac characteristics (40 mhz) (sheet 3 of 3) (80960cf-40 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes notes: see table 18 for all notes related to ac specifications.
preliminary 29 a 80960cf-40, -33, -25, -16 table 16. 80960cf ac characteristics (33 mhz) (sheet 1 of 3) (80960cf-33 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes input clock (1,9) t f clkin frequency 0 66.66 mhz t c clkin period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 30 15 125 ns ns (11) t cs clkin period stability in 1-x mode (f clk1x ) 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 5 5 62.5 ns ns (11) t cl clkin low time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 5 5 62.5 ns ns (11) t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1,8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) C 2 2 2 25 ns ns (3,12) (3) t pclk2:1 period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) tc 2tc ns ns (12) (3) t ph pclk2:1 high time (t/2) C 2 t/2 ns (12) t pl pclk2:1 low time (t/2) C 2 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) notes: see table 18 for all notes related to ac specifications.
30 preliminary 80960cf-40, -33, -25, -16 a synchronous outputs (8) t oh t ov output valid delay, output hold t oh1 , t ov1 a31:2 t oh2 , t ov2 be3:0 t oh3 , t ov3 ads t oh4 , t ov4 w/r t oh5 , t ov5 d/c , sup , dma t oh6 , t ov6 blast , wait t oh7 , t ov7 den t oh8 , t ov8 holda, breq t oh9 , t ov9 lock t oh10 , t ov10 dack3:0 t oh11 , t ov11 d31:0 t oh12 , t ov12 dt/r t oh13 , t ov13 fail t oh14 , t ov14 eop3:0 /tc3:0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 14 16 18 18 16 16 16 16 16 18 16 t/2 + 14 14 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) (6,10) t of output float for all outputs 3 22 ns (6) synchronous inputs (1,9,10) t is input setup tis1 d31:0 tis2 boff tis3 bterm /ready tis4 hold 3 17 7 7 ns ns ns ns t ih input hold tih1 d31:0 tih2 boff tih3 bterm /ready tih4 hold 5 5 2 3 ns ns ns ns relative output timings (1,2,3,8) t avsh1 a31:2 valid to ads rising t C 4 t + 4 ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t C 6 t + 6 ns t avel1 a31:2 valid to den falling t C 4 t + 4 ns t avel2 be3:0 , w/r , sup , inst ,dma , dack3:0 valid to den falling t C 6 t + 6 ns t nlqv wait falling to output data valid 6 ns table 16. 80960cf ac characteristics (33 mhz) (sheet 2 of 3) (80960cf-33 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes notes: see table 18 for all notes related to ac specifications.
preliminary 31 a 80960cf-40, -33, -25, -16 t dvnh output data valid to wait rising n*t C 6 n*t + 6 ns (4) t nlnh wait falling to wait rising n*t 4 ns (4) t nhqx output data hold after wait rising (n+1)*tC8 (n+1)*t+6 ns (5) t ehtv dt/r hold after den high t/2 C 7 ns (6) t tvel dt/r valid to den falling t/2 C 4 ns relative input timings (1,2,3) t is5 reset input setup (2-x clock mode) 6 ns (13) t ih5 reset input hold (2-x clock mode) 5 ns (13) t is6 dreq3:0 input setup 12 ns (7) t ih6 dreq3:0 input hold 7 ns (7) t is7 xint7:0 , nmi input setup 7 ns (15) t ih7 xint7:0 , nmi input hold 3 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 + 1 ns (14) table 16. 80960cf ac characteristics (33 mhz) (sheet 3 of 3) (80960cf-33 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes notes: see table 18 for all notes related to ac specifications.
32 preliminary 80960cf-40, -33, -25, -16 a table 17. 80960cf ac characteristics (25 mhz) (sheet 1 of 2) (80960cf-25 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max unit notes input clock (1,9) t f clkin frequency 0 50 mhz t c clkin period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 40 20 125 ns ns (11) t cs clkin period stability in 1-x mode (f clk1x ) 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 8 8 62.5 ns ns (11) t cl clkin low time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 8 8 62.5 ns ns (11) t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1,8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) C 2 2 2 25 ns ns (3,12) (3) t pclk2:1 period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) t c 2t c ns ns (12) (3) t ph pclk2:1 high time (t/2) C 3 t/2 ns (12) t pl pclk2:1 low time (t/2) C 3 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) synchronous outputs (8) t oh t ov output valid delay, output hold t oh1 , t ov1 a31:2 t oh2 , t ov2 be3:0 t oh3 , t ov3 ads t oh4 , t ov4 w/r t oh5 , t ov5 d/c , sup , dma t oh6 , t ov6 blast , wait t oh7 , t ov7 den t oh8 , t ov8 holda, breq t oh9 , t ov9 lock t oh10 , t ov10 dack3:0 t oh11 , t ov11 d31:0 t oh12 , t ov12 dt/r t oh13 , t ov13 fail t oh14 , t ov14 eop3:0 /tc3:0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 16 18 20 20 18 18 18 18 18 20 18 t/2 + 16 16 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) (6,10) t of output float for all outputs 3 22 ns (6) notes: see table 18 for all notes related to ac specifications.
preliminary 33 a 80960cf-40, -33, -25, -16 synchronous inputs (1,9,10) t is input setup t is1 d31:0 t is2 boff t is3 bterm /ready t is4 hold 5 19 9 9 ns ns ns ns t ih input hold t ih1 d31:0 t ih2 boff t ih3 bterm /ready t ih4 hold 5 7 2 5 ns ns ns ns relative output timings (1,2,3,8) t avs h1 a31:2 valid to ads rising t C 4 t + 4 ns t avs h2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t C 6 t + 6 ns t ave l1 a31:2 valid to den falling t C 4 t + 4 ns t ave l2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t C 6 t + 6 ns t nlqv wait falling to output data valid 6 ns t dvnh output data valid to wait rising n*t C f n*t + 6 ns (4) t nlnh wait falling to wait rising n*t 4 ns (4) t nhqx output data hold after wait rising (n+1)*tC 8 (n+1)*t+6 ns (5) t ehtv dt/r hold after den high t/2 C 7 ns (6) t tvel dt/r valid to den falling t/2 C 4 ns relative input timings (1,2,3) t is5 reset input setup (2-x clock mode) 8 ns (13) t ih5 reset input hold (2-x clock mode) 7 ns (13) t is6 dreq3:0 input setup 14 ns (7) t ih6 dreq3:0 input hold 9 ns (7) t is7 xint7:0 , nmi input setup 9 ns (15) t ih7 xint7:0 , nmi input hold 5 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 + 1 ns (14) table 17. 80960cf ac characteristics (25 mhz) (sheet 2 of 2) (80960cf-25 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max unit notes notes: see table 18 for all notes related to ac specifications.
34 preliminary 80960cf-40, -33, -25, -16 a table 18. 80960cf ac characteristics (16 mhz) (sheet 1 of 3) ( 80960CF-16 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes input clock (1,9) t f clkin frequency 0 32 mhz t c clkin period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 62.5 31.25 125 ns ns (11) t cs clkin period stability in 1-x mode (f clk1x ) 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 10 10 62.5 ns ns (11) t cl clkin low time in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) 10 10 62.5 ns ns (11) t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1,8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) C 2 2 2 25 ns ns (3,12) (3) t pclk2:1 period in 1-x mode (f clk1x ) in 2-x mode (f clk2x ) tc 2tc ns ns (12) (3) t ph pclk2:1 high time (t/2) C 4 t/2 ns (12) t pl pclk2:1 low time (t/2) C 4 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) synchronous outputs (8) t oh t ov output valid delay, output hold t oh1 , t ov1 a31:2 t oh2 , t ov2 be3:0 t oh3 , t ov3 ads t oh4 , t ov4 w/r t oh5 , t ov5 d/c , sup , dma t oh6 , t ov6 blast , wait t oh7 , t ov7 den t oh8 , t ov8 holda, breq t oh9 , t ov9 lock t oh10 , t ov10 dack3:0 t oh11 , t ov11 d31:0 t oh12 , t ov12 dt/r t oh13 , t ov13 fail t oh14 , t ov14 eop3:0 /tc3:0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 18 20 22 22 20 20 20 20 20 22 20 t/2 + 18 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) (6,10) t of output float for all outputs 3 22 ns (6)
preliminary 35 a 80960cf-40, -33, -25, -16 synchronous inputs (1,9,10) t is input setup t is1 d31:0 t is2 boff t is3 bterm /ready t is4 hold 5 21 9 9 ns ns ns ns t ih input hold t ih1 d31:0 t ih2 boff t ih3 bterm /ready t ih4 hold 5 7 2 5 ns ns ns ns relative output timings (1,2,3,8) t avs h1 a31:2 valid to ads rising t C 4 t + 4 ns t avs h2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t C 6 t + 6 ns t ave l1 a31:2 valid to den falling t C 6 t + 6 ns t ave l2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t C 6 t + 6 ns t nlqv wait falling to output data valid 6 ns t dvnh output data valid to wait rising n*t C 6 n*t + 6 ns (4) t nlnh wait falling to wait rising n*t 4 ns (4) t nhqx output data hold after wait rising (n+1)*tC8 (n+1)*t+6 ns (5) t ehtv dt/r hold after den high t/2 C 7 ns (6) t tvel dt/r valid to den falling t/2 C 4 ns relative input timings (1,2,3) t is5 reset input setup (2-x clock mode) 10 ns (13) t ih5 reset input hold (2-x clock mode) 9 ns (13) t is6 dreq3:0 input setup 16 ns (7) t ih6 dreq3:0 input hold 11 ns (7) t is7 xint7:0 , nmi input setup 9 ns (15) table 18. 80960cf ac characteristics (16 mhz) (sheet 2 of 3) ( 80960CF-16 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes
36 preliminary 80960cf-40, -33, -25, -16 a 4.5.1 ac test conditions the ac specifications in section 4.5 are tested with the 50 pf load shown in figure 7. figure 16 shows how timings vary with load capacitance. specifications are measured at the 1.5v crossing point, unless otherwise indicated. input waveforms are assumed to have a rise and fall time of 2 ns from 0.8v to 2.0v. see section 4.5.2, ac timing waveforms for ac specification definitions, test points and illustrations. t ih7 xint7:0 , nmi input hold 5 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 + 1 ns (14) notes: 1. see section 4.5.2, ac timing waveforms for waveforms and definitions. 2. see figure 16 for capacitive derating information for output delays and hold times. 3. see figure 17 for capacitive derating information for rise and fall times. 4. where n is the number of nrad, nrdd, nwad or nwdd wait states that are programmed in the bus controller region table. wait never goes active when there are no wait states in an access. 5. n = number of wait states inserted with ready. 6. output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. since asynchronous inputs are synchronized internally by the 80960cf, they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. 8. these specifications are guaranteed by the processor. 9. these specifications must be met by the system for proper operation of the processor. 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curves to adjust the timing for pclk2:1 loading. 11. in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% between adjacent cycles. 13. in 2-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 23.) 14. in 1-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the rising edge of the clkin. (see figure 24.) 15. the interrupt pins are synchronized internally by the 80960cf. they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three con- secutive pclk2:1 rising edges when asserting them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive pclk2:1 rising edges. table 18. 80960cf ac characteristics (16 mhz) (sheet 3 of 3) ( 80960CF-16 only, per the conditions in 4.2 operating conditions and 4.5.1 ac test conditions .) symbol parameter min max units notes
preliminary 37 a 80960cf-40, -33, -25, -16 figure 7. ac test load 4.5.2 ac timing waveforms figure 8. input and output clocks waveform figure 9. clkin waveform output pin c l = 50 pf for all signals c l f_cx008a pclk2:1 2.4 v 1.5 v 1.5 v 1.5 v 0.45 v t cp t ph t pl t pr t pf t f_cx009a clkin 2.0 v 1.5 v 0.8 v t cf t ch t cl t c t cr f_cx010a
38 preliminary 80960cf-40, -33, -25, -16 a figure 10. output delay and float waveform figure 11. input setup and hold waveform pclk2:1 outputs 1.5 v 1.5 v t ov min max t oh min max t of 1.5 v 1.5 v 1.5 v 1.5 v outputs f_cx011a notes: 1. t ov t oh - output delay - maximum output delay is referred to as output valid delay (t ov ); minimum output delay is referred to as output hold (t oh ). 2. t of - output float delay - output float condition occurs when the maximum output current becomes less that i lo in magnitude. pclk2:1 inputs: 1.5 v 1.5 v 1.5 v valid t is t ih (ready , hold, bterm , boff , dreq3:0 , d31:0 on reads) f_cx012a min max notes: 1. t is t ih - input setup and hold - the input setup and hold requirements specify the sampling win-
preliminary 39 a 80960cf-40, -33, -25, -16 figure 12. nmi , xint7:0 input setup and hold waveform figure 13. hold acknowledge timings pclk2:1 1.5 v 1.5 v 1.5 v valid t is t ih nmi , xint7:0 min min f_cx013a 1.5 v 1.5 v pclk2:1 1.5 v 1.5 v 1.5 v outputs: a31:2, d31:0, be3:0 , ads , blast , wait , w/r , dt/r , den , lock , d/c , sup , dma min max min max valid 1.5 v valid t of t ov hold t is t ih 1.5 v 1.5 v t ih t is holda t ov min min min min max min max min f_cx014a 1.5 v 1.5 v 1.5 v notes: 1. t ov t oh - output delay - maximum output delay is referred to as output valid delay (t ov ); minimum output delay is referred to as output hold (t oh ). 2. t of - output float delay - output float condition occurs when the maximum output current becomes less that i lo in magnitude. 3. t is t ih - input setup and hold - the input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 1.5 v t ov
40 preliminary 80960cf-40, -33, -25, -16 a figure 14. bus backoff (boff ) timings figure 15. relative timings waveforms pclk2:1 1.5 v 1.5 v 1.5 v outputs: a31:2, d31:0, be3:0 , ads , blast , wait , w/r , dt/r , den , lock , d/c , sup , dma min max min max valid 1.5 v valid t of t ov boff t is t ih 1.5 v 1.5 v 1.5 v t ih t is f_cx015a 1.5 v 1.5 v pclk2:1 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t avsh t dvnh t nhqx t nlnh t avel t vel t ehtv t nlqv ads a31:2, be3:0 , w/r , lock , sup , d/c , dma d31:0 wait dt/r den d31:0 f_cx016a 1.5 v in v ih v il out
preliminary 41 a 80960cf-40, -33, -25, -16 4.5.3 derating curves figure 16. output delay or hold vs. load capacitance figure 17. rise and fall time derating at highest operating temperature and minimum v cc 50 100 150 c l (pf) nom + 10 nom + 5 nom all outputs except: lock , eop3:0 / tc3:0 , fail f_cx017a dma , sup , breq, dack3:0 , note : pclk load = 50pf lock , dma , sup , breq, dack3:0 , eop3:0 /tc3:0 , fail 50 100 150 c l (pf) 10 8 6 4 2 50 100 150 c l (pf) 10 8 6 4 2 a) all outputs except: lock , dma , sup , holda, breq dack3:0 , eop3:0 / tc3:0 , fail b) lock , dma , sup , holda, breq, dack3:0 , eop3:0 /tc3:0 , fail 0.8 v to 2.0 v 0.8v to 2.0v f_cx019a
42 preliminary 80960cf-40, -33, -25, -16 a figure 18. i cc vs. frequency and temperature80960cf-33, -25, -16 figure 19. i cc vs. frequency and temperature80960cf-40 900 0 0 33 t c = 100 c t c = 0 c f pclk (mhz) i cc - i cc under test conditions f_cx020a 1100 0 0 40 f pclk (mhz) i cc - i cc under test conditions f_cx020a t c = t c = 85 c 5.0 reset, backoff and hold acknowledge table 19 lists the condition of each processor output pin while reset is asserted (low). table 20 lists the condition of each processor output pin while holda is asserted (high). in table 20, with regard to bus output pin state only, the hold acknowledge state takes precedence over the reset state. although asserting the reset pin internally resets the processor, the processors bus output pins do not enter the reset state if hold acknowledge has been granted to a previous hold request (holda is active). furthermore, the processor grants new hold requests and enters the hold acknowledge state even while in reset. for example, if hold is asserted while holda is inactive and the processor is in the reset state, the processors bus pins enter the hold acknowledge state and holda is granted. the processor is not able to perform memory accesses until the hold request is removed, even if the reset pin is brought high. this operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus.
a 80960cf-40, -33, -25, -16 preliminary 43 table 19. reset conditions pins state during reset (holda inactive) a31:2 floating d31:0 floating be3:0 driven high (inactive) w/r driven low (read) ads driven high (inactive) wait driven high (inactive) blast driven low (active) dt/r driven low (receive) den driven high (inactive) lock driven high (inactive) breq driven low (inactive) d/c floating dma floating sup floating fail driven low (active) dack3:0 driven high (inactive) eop3:0 /tc3:0 floating (set to input mode) table 20. hold acknowledge and backoff conditions pins state during holda a31:2 floating d31:0 floating be3:0 floating w/r floating ads floating wait floating blast floating dt/r floating den floating lock floating breq driven (high or low) d/c floating dma floating sup floating fail driven high (inactive) dack3:0 driven high (inactive) eop3:0 /tc3:0 driven (if output)
44 preliminary 80960cf-40, -33, -25, -16 a 6.0 bus waveforms figure 20. cold reset waveform
preliminary 45 a 80960cf-40, -33, -25, -16 figure 21. warm reset waveform
46 preliminary 80960cf-40, -33, -25, -16 a figure 22. entering the once state
preliminary 47 a 80960cf-40, -33, -25, -16 figure 23. clock synchronization in the 2-x clock mode figure 24. clock synchronization in the 1-x clock mode clkin reset pclk2:1 (case 1) pclk2:1 (case 2) 1.5 v t ih t is 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t cp max min t cp max min t cp sync note : case 1 and case 2 show two possible polarities of pclk2:1 min 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v f_cx024a max clkin 1.5 v 1.5 v reset t ih t is 1.5 v 2x clk note : in 1x clock mode, the reset pin is actually sampled on the falling edge of 2xclk. 2xclk is an internal signal generated by the pll and is not available on an external pin. therefore, reset is specified relative to the rising edge of clkin. the reset pin is sampled when pclk is high. f_cx025a
48 preliminary 80960cf-40, -33, -25, -16 a figure 25. non-burst, non-pipelined requests without wait states in ads a31:4, sup , dma , d/c , be3:0 , lock w / r blast dt / r den a3:2 wait d31:0 pclk ad ad ad in valid valid valid valid valid byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 x x xx 0 00000 x xx 0 00000 off 0 disabled 0 0 0..0 disabled 0 valid f_cx026a out function bit value xx
preliminary 49 a 80960cf-40, -33, -25, -16 figure 26. non-burst, non-pipelined read request with wait states ads a31:2, be3:0 dma , d/c , sup , lock w/r blast dt/r den wait d31:0 pclk a3 21 d1 byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 x xx x xx x xxxxx x xx 3 00011 off 0 disabled 0 0 0..0 disabled 0 in function bit value valid valid a f_cx027a
50 preliminary 80960cf-40, -33, -25, -16 a figure 27. non-burst, non-pipelined write request with wait states ads a31:2, w/r blast dt/r den sup , dma , wait d31:0 pclk a3 2 1 d1 byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11 - 10 9 -8 2 1 0 x x 0 0 1 01 x xx x xx 3 00011 x xx x xxxxxx off 0 disabled 0 0 0..0 disabled 0 out a function bit value valid valid d/c , lock f_cx028a be3:0
preliminary 51 a 80960cf-40, -33, -25, -16 figure 28. burst, non-pipelined read request without wait states, 32-bit bus in0 ads a31:4, sup, dma , d/c , be3:0 , lock w / r blast dt / r den a3:2 wait d31:0 pclk ad dd da byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 32-bit 10 x xx x xxxxx 0 00 0 00000 off 0 enabled 1 0 0..0 disabled 0 f_cx029a function bit value in3 in2 in1 valid 00 01 10 11
52 preliminary 80960cf-40, -33, -25, -16 a figure 29. burst, non-pipelined read request with wait states, 32-bit bus ads a31:4, sup , dma , d/c, be3:0 , lock w/r blast dt/r den a3:2 wait d31:0 pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 32-bit 10 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a21 d 1 d 1 d 1d 1 a in1 in2 in3 in0 valid 00 11 01 10 function bit value f_cx030a
preliminary 53 a 80960cf-40, -33, -25, -16 figure 30. burst, non-pipelined write request without wait states, 32-bit bus byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 32-bit 10 0 00 0 00000 x xx x xxxxx off 0 enabled 1 0 0..0 disabled 0 ads a31:4, sup , dma , d/c , be3:0 , lock w / r blast dt / r den a3:2 wait d31:0 pclk ad dd da function bit value 00 01 10 11 out0 valid out3 out2 out1 f_cx031a
54 preliminary 80960cf-40, -33, -25, -16 a figure 31. burst, non-pipelined write request with wait states, 32-bit bus ads a31:4, sup , dma , d/c , be3:0 , lock w/r blast dt/r den a3:2 wait d31:0 pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 32-bit 10 1 01 2 00010 x xx x xxxxx off 0 enabled 1 0 0..0 disabled 0 a2 1 d 1 d 1 d 1d 1 a out0 valid 00 11 01 10 function bit value out1 out2 out3 f_cx032a
preliminary 55 a 80960cf-40, -33, -25, -16 figure 32. burst, non-pipelined read request with wait states, 16-bit bus ads sup , dma , w/r blast dt/r den a3:2 wait d31:0 pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 16-bit 01 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a2 1 d 1d 1 d 1d 1 a function bit value valid a3:2 = 00 or 10 a3:2 = 01 or 11 d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d/c , lock , a31:4, be3 /bhe, be1 /a1 be0 /ble f_cx033a
56 preliminary 80960cf-40, -33, -25, -16 a figure 33. burst, non-pipelined read request with wait states, 8-bit bus ads sup , dma , w/r blast dt/r den a3:2 wait d31:0 pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 8-bit 00 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a2 1 d 1 d 1 d 1d 1 a function bit value vali d a3:2 = 00, 01, 10 or 11 d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d/c , lock , a31:4 be1 /a1, a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 =11 be0 /a0 f_cx034a
preliminary 57 a 80960cf-40, -33, -25, -16 figure 34. non-burst, pipelined read request without wait states, 32-bit bus non-pipelined request concludes pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. ads a31:4, sup , dma , d/c , lock blast wait d31:0 pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx x xx x xx x xxxxx x xx 0 00000 on 1 disabled 0 0 0..0 x x function bit value in d in d' in d'' in d''' in d'''' aa' d a'' d' a''' d'' a'''' d''' d'''' valid valid valid valid valid invalid invalid dt/r den a3:2 be3:0 valid valid valid valid valid invalid w/r f_cx035a
58 preliminary 80960cf-40, -33, -25, -16 a figure 35. non-burst, pipelined read request with wait states, 32-bit bus non-pipelined request concludes pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. ads a31:4, sup , dma , d/c , w/r blast dt/r den a3:2 wait d31:0 pclk be3:0 a1 a' d 1d' byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx x xx x xx x xxxxx x xx 1 00001 on 1 disabled 1 0 0..0 x x in d' invalid valid valid invalid in d lock valid valid invalid function bit value f_cx036a
preliminary 59 a 80960cf-40, -33, -25, -16 figure 36. burst, pipelined read request without wait states, 32-bit bus pipelined reads conclude, non-pipelined requests begin ads a31:4, sup , dma , d/c , be3:0 , lock w/r blast dt/r den a3:2 wait d31:0 pclk non-pipelined request concludes, pipelined reads begin byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-109-8 210 x x 0 0 x xx 32-bit 10 x xx x xxxxx 0 00 0 00000 on 1 enabled 1 0 0..0 disabled 0 addda' d' d' valid valid in- valid valid 01 10 11 00 in d in d in d in d in d in d valid d function bit value in- valid in- valid f_cx037a
60 preliminary 80960cf-40, -33, -25, -16 a figure 37. burst, pipelined read request with wait states, 32-bit bus ads a31:4, sup , dma , d/c , be3:0 , lock w/r a3:2 d31:0 wait blast dt/r den pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11 - 10 9 -8 2 1 0 x x 0 0 x xx 32-bit 10 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value in d in d in d in d in d' a21 d 1 d 1 d 1a'2 1 valid d d' valid in- valid in- valid 00 01 10 11 valid in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. f_cx038a
preliminary 61 a 80960cf-40, -33, -25, -16 figure 38. burst, pipelined read request with wait states, 16-bit bus ads a31:4, sup , dma , d/c , be0 /ble , w/r a3:2 be1 /a1 wait blast dt/r den pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 16-bit 01 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d15:0 d' a2 1 d 1 d 1 d 1a'2 1 d d' in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. a3:2 = 00 or 10 a3:2 = 01 or 11 valid in- valid valid in- valid be3 /bhe, d31:0 f_cx040a lock val id valid in- valid
62 preliminary 80960cf-40, -33, -25, -16 a figure 39. burst, pipelined read request with wait states, 8-bit bus ads a31:4, sup , dma , d/c , lock w/r a3:2 be1 /a1, wait blast dt/r den pclk byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external ready control burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 8-bit 00 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d7:0 d' a2 1 d 1 d 1 d 1a'2 1 d d' in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. valid in- valid be0 /a0 d31:0 a3:2 = 00, 01, 10, or 11 valid in- valid a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 = 11 valid valid in- valid f_cx039a
preliminary 63 a 80960cf-40, -33, -25, -16 figure 40. using external ready pclk ads a31:4, sup , dt/r den ready w/r dma , inst , blast bterm a3:2 wait d31:0 d/c , be3:0 , lock d0 d1 d2 d3 d0 d1 d2 d3 00 01 10 11 00 01 10 11 valid valid quad-word read request n rad = 0, n rdd = 0, n xda = 0 ready enabled quad-word write request n wad = 1, n wdd = 0, n wda = 0 ready enabled f_cx041a
64 preliminary 80960cf-40, -33, -25, -16 a figure 41. terminating a burst with bterm pclk ads a31:4, sup , dt/r den ready w/r dma , inst, blast bterm a3:2 wait d31:0 d/c , be3:0 , lock d0 d1 d2 d3 valid quad-word write request n wad = 0, n wdd = 0, n wda = 0 ready enabled 00 01 10 11 note : ready adds memory access time to data transfers, whether or not the bus access is a burst access. bterm interrupts a bus access, whether or not the bus access has more data transfers pending. either the ready signal or the bterm signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. see note f_cx042a
preliminary 65 a 80960cf-40, -33, -25, -16 figure 42. boff functional timing ads blast ready boff a31:2, sup , d31:0, boff may not be asserted boff may not be asserted boff may be asserted to suspend request begin request end request suspend request non-burst regenerate ads dma , d/c , be3:0 , wait , den , dt/r (writes) burst resume request burst note: ready /bterm must be enabled; n rad , n rdd , n wad , n wdd = 0 f_cx043a may change
66 preliminary 80960cf-40, -33, -25, -16 a figure 43. hold functional timing word read request n rad =1, n xda =1 word read request n rad =0, n xda =0 hold state hold state pclk2:1 ads a31:2, sup , dma , d/c , be3:0 , wait , den , dt/r blast hold holda valid valid f_cx044a
preliminary 67 a 80960cf-40, -33, -25, -16 figure 44. dreq and dack functional timing figure 45. eop functional timing pclk2:1 ads ! ( blast & ready dackx (all modes) dreqx (case 1) dreqx (case 2) note: f_cx018a & !wait ) system clock start dma bus request end dma bus request dma acknowledge dma request t is6 t ih6 t is6 t ih6 (see note) 1. case 1: dreq must deassert before dack deasserts. this applies to all fly-by modes: source synchronized packing modes and destination synchronized unpacking modes. 2. case 2: dreq must be deasserted by the second clock (rising edge) after dack is driven high. this applies to all other dma transfers. 3. dackx is asserted for the duration of a dma bus request. the request may consist of multiple bus accesses (defined by ads and blast ). high to prevent next bus cycle high to prevent next bus cycle pclk2:1 eop f_cx045a note : eop has the same ac timing requirements as dreq to prevent unwanted dma requests. eop is not edge held for a minimum of 2 clock cycles then deasserted within 15 clock cycles. triggered. eop must be 15 clks max 2 clks min
68 preliminary 80960cf-40, -33, -25, -16 a figure 46. terminal count functional timing figure 47. fail functional timing note : terminal count becomes active during the last bus request of a buffer transfer. if the last load/store bus request is executed as multiple bus accesses, the tc will be active for the entire bus request. refer to the i960? cx microprocessor users manual for further information. pclk2:1 dreq ads dack tc f_cx046a reset fail ~65,000 cycles 5 cycles 102 cycles (bus test) pass (internal self-test) pass fail fail f_cx047a
preliminary 69 a 80960cf-40, -33, -25, -16 figure 48. a summary of aligned and unaligned transfers for little endian regions 04 812162024 01 234 5 6 one double-word short-word load/store word load/store double-word load/store byte, byte requests short request (aligned) short request (aligned) byte, byte requests word request (aligned) byte, short, byte, requests short, short requests byte, short, byte requests byte offset word offset f_cx048a one double-word burst (aligned) byte, short, word, byte requests short, word, short requests byte, word, short, byte requests word, word requests request (aligned)
70 preliminary 80960cf-40, -33, -25, -16 a figure 49. a summary of aligned and unaligned transfers for little endian regions (continued) 04 812162024 0123456 triple-word load/store quad-word load/store word, word, word requests requests double- double- word, word, word, word requests byte offset word offset one three-word request (aligned) byte, short, word, word, byte requests short requests short, word, word, byte, word, word, short, byte requests word, word, word requests one four-word request (aligned) byte, short, word, word, word, byte requests short, word, word, word, short requests byte, word, word, word, short, byte requests f_cx049a requests word, word word, word, word,
preliminary 71 a 80960cf-40, -33, -25, -16 figure 50. idle bus operation 7.0 revision history this is a new data sheet for the 80960cf-40 product. it is derived from the 80960cf-33, -25, -16 data sheet. aside from a few minor edits, only the ac characteristics differ from the 80960cf-33, -25, -16 data sheet. pclk ads a31:4, sup , dma , inst, d/c , be3:0 lock w/r blast dt/r den a3:2 wait d31:0 ready , bterm write request n wad =2, n xda = 0 ready disabled idle bus (not in hold acknowledge state) read request n wad =2, n xda = 0 ready disabled in out valid valid valid valid valid valid f_cx050a

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